Capacitance-voltage technique for characterization of lateral trap locations along the channel in low-temperature poly-silicon thin film transistors
Yoo, Han Bin, Kim, Junyeap, Yu, Jintae, Kim, Hyo-Jin, Choi, Sung-Jin, Kim, Dae Hwan, Kim, Dong MyongVolume:
163
Language:
english
Journal:
Solid-State Electronics
DOI:
10.1016/j.sse.2019.107647
Date:
January, 2020
File:
PDF, 3.50 MB
english, 2020