Experimental Demonstration of Stacked Gate-All-Around...

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IEEE Electron Device Letters 2019

Experimental Demonstration of Stacked Gate-All-Around Poly-Si Nanowires Negative Capacitance FETs with Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process

Lee, Shen-Yang, Chen, Han-Wei, Shen, Chiuan-Huei, Kuo, Po-Yi, Chung, Chun-Chih, Huang, Yu-En, Chen, Hsin-Yu, Chao, Tien-Sheng
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Year:
2019
Journal:
IEEE Electron Device Letters
DOI:
10.1109/LED.2019.2940696
File:
PDF, 634 KB
2019
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