A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time...

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IEEE Journal of Solid-State Circuits 2019

A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power

Santiccioli, Alessio, Mercandelli, Mario, Lacaita, Andrea L., Samori, Carlo, Levantino, Salvatore
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Year:
2019
Language:
english
Journal:
IEEE Journal of Solid-State Circuits
DOI:
10.1109/JSSC.2019.2941259
File:
PDF, 3.21 MB
english, 2019
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