Design and simulation of vertically-stacked nanowire...

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Physica Scripta 2019 / 09

Design and simulation of vertically-stacked nanowire transistors at 3nm technology nodes

Dey, Suprava, Jena, J R, Mohapatra, E, Dash, Taraprasanna, Das, Sanghamitra, Maiti, C K
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Language:
english
Journal:
Physica Scripta
DOI:
10.1088/1402-4896/ab4621
Date:
September, 2019
File:
PDF, 876 KB
english, 2019
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