Simulation of the Effect of Parasitic Channel Height on...

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Solid-State Electronics 2019 / 10

Simulation of the Effect of Parasitic Channel Height on Characteristics of Stacked Gate-All-Around Nanosheet FET

Choi, Yunho, Lee, Kitae, Yeon Kim, Kyoung, Kim, Sihyun, Lee, Junil, Lee, Ryoongbin, Kim, Hyun-Min, Suh Song, Young, Kim, Sangwan, Lee, Jong-Ho, Park, Byung-Gook
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Language:
english
Journal:
Solid-State Electronics
DOI:
10.1016/j.sse.2019.107686
Date:
October, 2019
File:
PDF, 1.12 MB
english, 2019
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