Design and Performance of 155 Mbps Clock/Data Recovery...

Analog Integrated Circuits and Signal Processing 2005 / 05 Vol. 43; Iss. 2

Design and Performance of 155 Mbps Clock/Data Recovery Circuits on Heavy Loaded PLDs

Rui L. Aguiar, Mónica Figueiredo
How much do you like this book?
What’s the quality of the file?
Download the book for quality assessment
What’s the quality of the downloaded files?
Volume:
43
Language:
english
Pages:
12
DOI:
10.1007/s10470-005-6789-y
Date:
May, 2005
File:
PDF, 1.67 MB
english, 2005
Conversion to is in progress
Conversion to is failed