Design of output buffer with low switching noise and load...

Analog Integrated Circuits and Signal Processing 2010 / 11 Vol. 65; Iss. 2

Design of output buffer with low switching noise and load adaptability

Yingyan Lin, Jing Zhang, Xuecheng Zou, Dongsheng Liu, Shuang-yang Wang
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Volume:
65
Language:
english
Pages:
10
DOI:
10.1007/s10470-010-9469-5
Date:
November, 2010
File:
PDF, 504 KB
english, 2010
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