Symbolic noise modeling, analysis and optimization of a...

Analog Integrated Circuits and Signal Processing 2012 / 03 Vol. 70; Iss. 3

Symbolic noise modeling, analysis and optimization of a CMOS input buffer

Santosh Kumar Patnaik, Swapna Banerjee
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Volume:
70
Language:
english
Pages:
10
DOI:
10.1007/s10470-011-9688-4
Date:
March, 2012
File:
PDF, 620 KB
english, 2012
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