Low power radiation aware transistor level design using...

IET Circuits Devices & Systems 2019 / 10 Vol. 13; Iss. 7

Low power radiation aware transistor level design using tri-state inverter embedded non-clock gating technique

Kamalakannan, Ramaian Subramanian, Venkatachalam, Kuppusamy
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Volume:
13
Journal:
IET Circuits, Devices & Systems
DOI:
10.1049/iet-cds.2018.5232
Date:
October, 2019
File:
PDF, 1.60 MB
2019
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