A PARALLEL COUPLED-LINE FILTER USING VLSI BACKEND INTERCONNECT WITH HIGH RESISTIVITY SUBSTRATE
C. C. Chen, H. L. Kao, K. C. Chiang, Albert ChinVolume:
27
Language:
english
Pages:
13
DOI:
10.1007/s10762-006-9051-5
Date:
January, 2006
File:
PDF, 193 KB
english, 2006