Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG
Andreas Veneris, Robert Chang, Magdy S. Abadir, Sep SeyediVolume:
21
Language:
english
Pages:
8
DOI:
10.1007/s10836-005-1543-z
Date:
October, 2005
File:
PDF, 861 KB
english, 2005