A Gated Clock Scheme for Low Power Testing of Logic Cores

Journal of Electronic Testing 2006 / 02 Vol. 22; Iss. 1

A Gated Clock Scheme for Low Power Testing of Logic Cores

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
How much do you like this book?
What’s the quality of the file?
Download the book for quality assessment
What’s the quality of the downloaded files?
Volume:
22
Language:
english
Pages:
11
DOI:
10.1007/s10836-006-6259-1
Date:
February, 2006
File:
PDF, 289 KB
english, 2006
Conversion to is in progress
Conversion to is failed