Scheduling Tests for 3D Stacked Chips under Power...

Scheduling Tests for 3D Stacked Chips under Power Constraints

Breeta SenGupta, Urban Ingelsson, Erik Larsson
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Volume:
28
Language:
english
Pages:
15
DOI:
10.1007/s10836-011-5244-5
Date:
February, 2012
File:
PDF, 579 KB
english, 2012
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