A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc...

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IEEE Journal of Solid-State Circuits 2020

A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control

Ko, Chen-Ting, Kuan, Ting-Kuei, Shen, Ruei-Pin, Chang, Chih-Hsien
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Year:
2020
Journal:
IEEE Journal of Solid-State Circuits
DOI:
10.1109/JSSC.2019.2959735
File:
PDF, 3.48 MB
2020
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