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A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS
Ramkaj, Athanasios T., Pena Ramos, Juan C., Pelgrom, Marcel J. M., Steyaert, Michiel S. J., Verhelst, Marian, Tavernier, FilipYear:
2020
Journal:
IEEE Journal of Solid-State Circuits
DOI:
10.1109/JSSC.2019.2960476
File:
PDF, 4.89 MB
2020