Enhancing Temporal Logic Falsification with Specification Transformation and Valued Booleans
Eddeland, Johan Liden, Claessen, Koen, Smallbone, Nicholas, Ramezani, Zahra, Miremadi, Sajed, Akesson, KnutYear:
2020
Journal:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOI:
10.1109/TCAD.2020.2966480
File:
PDF, 366 KB
2020