High data-rate readout logic design of a 512 × 1024 pixel...

Journal of Instrumentation 2019 / 12 Vol. 14; Iss. 12

High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector

Wei, X., Wei, W., Wu, T., Zhang, Y., Li, X., Zhang, L., Lu, W., Liang, Z., Dong, J., Li, L., Wang, J., Zheng, R., Casanova, R., Grinstein, S., Hu, Y., Costa, J. Guimaraes da
How much do you like this book?
What’s the quality of the file?
Download the book for quality assessment
What’s the quality of the downloaded files?
Volume:
14
Language:
english
Journal:
Journal of Instrumentation
DOI:
10.1088/1748-0221/14/12/C12012
Date:
December, 2019
File:
PDF, 758 KB
english, 2019
Conversion to is in progress
Conversion to is failed