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[IEEE 2019 Symposium on VLSI Technology - Kyoto, Japan (2019.6.9-2019.6.14)] 2019 Symposium on VLSI Technology - A record Gm SAT /SS SAT and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparation
Arimura, H., Cott, D., Boccardi, G., Loo, R., Wostyn, K., Brus, S., Capogreco, E., Opdebeeck, A., Witters, L., Conard, T., Suhard, S., Van Dorp, D., Kenis, K., Ragnarsson, L.-A., Mitard, J., HolsteynsYear:
2019
Language:
english
DOI:
10.23919/VLSIT.2019.8776535
File:
PDF, 2.38 MB
english, 2019