PUF-Based Secure Chaotic Random Number Generator Design...

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2020

PUF-Based Secure Chaotic Random Number Generator Design Methodology

Kalanadhabhatta, Srisubha, Kumar, Deepak, Anumandla, Kiran Kumar, Reddy, S. Ashish, Acharyya, Amit
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Year:
2020
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2020.2979269
File:
PDF, 1.33 MB
2020
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