![](/img/cover-not-exists.png)
A 0.2-1.3 ns Range Delay-Control Scheme for a 25 Gb/s Data-Receiver Using a Replica Delay-Line-Based Delay-Locked-Loop in 45-nm CMOS
Rehman, Sami Ur, Khafaji, Mohammad Mahdi, Ferschischi, Ali, Carta, Corrado, Ellinger, FrankVolume:
67
Journal:
IEEE Transactions on Circuits and Systems II: Express Briefs
DOI:
10.1109/tcsii.2020.2980813
Date:
May, 2020
File:
PDF, 2.49 MB
2020