A Signed Array Multiplier with Bypassing Logic

Journal of Signal Processing Systems 2012 / 02 Vol. 66; Iss. 2

A Signed Array Multiplier with Bypassing Logic

Chua-Chin Wang, Chia-Hao Hsu, Gang-Neng Sung, Yu-Cheng Lu
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Volume:
66
Language:
english
Pages:
6
DOI:
10.1007/s11265-010-0558-6
Date:
February, 2012
File:
PDF, 545 KB
english, 2012
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