A Statistical Gate Sizing Method for Timing Yield and...

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A Statistical Gate Sizing Method for Timing Yield and Lifetime Reliability Optimization of Integrated Circuits

Ibrahimi, S. Milad, Ghavami, Behnam, Raji, Mohsen
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Year:
2020
Journal:
IEEE Transactions on Emerging Topics in Computing
DOI:
10.1109/TETC.2020.2987946
File:
PDF, 351 KB
2020
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