High-Speed Hybrid-Logic Full Adder Using High-Performance...

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2020

High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T xor-xnor Cell

Kandpal, Jyoti, Tomar, Abhishek, Agarwal, Mayur, Sharma, K. K.
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Year:
2020
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2020.2983850
File:
PDF, 1.20 MB
2020
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