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[IEEE 2019 53rd Asilomar Conference on Signals, Systems, and Computers - Pacific Grove, CA, USA (2019.11.3-2019.11.6)] 2019 53rd Asilomar Conference on Signals, Systems, and Computers - FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation
Palchaudhuri, Ayan, Dhar, Anindya SundarYear:
2019
DOI:
10.1109/ieeeconf44664.2019.9049071
File:
PDF, 1.48 MB
2019