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[IEEE 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS) - San Jose, Costa Rica (2020.2.25-2020.2.28)] 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS) - Gate Sizing for Power-Delay Optimization at Transistor-level Monolithic 3D-Integrated Circuits
Zanelli, Juliano C., Metzler, Carolina, Reis, RicardoYear:
2020
DOI:
10.1109/LASCAS45839.2020.9069042
File:
PDF, 117 KB
2020