Design of area efficient VLSI...

Computational Intelligence 2020 / 05

Design of area efficient VLSI architecture for carry select adder using logic optimization technique

Kandula, Bala Sindhuri, Kalluru, Padma Vasavi, Inty, Santi Prabha
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Journal:
Computational Intelligence
DOI:
10.1111/coin.12347
Date:
May, 2020
File:
PDF, 2.36 MB
2020
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