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[IEEE 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) - Hsinchu, Taiwan (2020.8.10-2020.8.13)] 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) - Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers
Lin, Chia-Chen, Wu, Yi-Jui, You, Wei-Xiang, Su, PinYear:
2020
DOI:
10.1109/VLSI-TSA48913.2020.9203647
File:
PDF, 933 KB
2020