A 1.8-nW, -73.5-dB PSRR, 0.2-ms Startup Time, CMOS Voltage...

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IEEE Journal of Solid-State Circuits 2020

A 1.8-nW, -73.5-dB PSRR, 0.2-ms Startup Time, CMOS Voltage Reference With Self-Biased Feedback and Capacitively Coupled Schemes

Shao, Cheng-Ze, Kuo, Shih-Che, Liao, Yu-Te
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Year:
2020
Journal:
IEEE Journal of Solid-State Circuits
DOI:
10.1109/jssc.2020.3028506
File:
PDF, 6.31 MB
2020
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