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IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2020

Automatic Floorplanning and Standalone Generation of Bitstream-Level IP Cores

Khan, Nadir, Castro-Godinez, Jorge, Xue, Shixiang, Henkel, Jorg, Becker, Jurgen
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Year:
2020
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/tvlsi.2020.3023548
File:
PDF, 1.59 MB
2020
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