Gate drive circuit for current balancing of parallel-connected SiC-JFETs under avalanche mode
Takamori, Taro, Wada, Keiji, Saito, Wataru, Nishizawa, Shin-ichiJournal:
Microelectronics Reliability
DOI:
10.1016/j.microrel.2020.113776
Date:
November, 2020
File:
PDF, 893 KB
2020