Efficient hardware architecture for integer implementation...

Efficient hardware architecture for integer implementation of multi-alphabet arithmetic coding for data mining

Jayavathi, S.D., Shenbagavalli, A., Ram, B. Ganapathy
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Volume:
13
Year:
2018
Journal:
International Journal of Business Intelligence and Data Mining
DOI:
10.1504/ijbidm.2018.088432
File:
PDF, 727 KB
2018
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