Design of multiplier for arithmetic-high-level synthesis...

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Design of multiplier for arithmetic-high-level synthesis using modified booth encoding

Supritha, B., Kiran, M., Veera Reddy, B., Jamal, K., Kumar, Manchalla O.V.P.
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Journal:
Materials Today: Proceedings
DOI:
10.1016/j.matpr.2020.10.460
Date:
December, 2020
File:
PDF, 1.87 MB
2020
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