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Bias-stress induced threshold voltage and drain current instability in 4H–SiC DMOSFETs
T. Okayama, S.D. Arthur, J.L. Garrett, M.V. RaoVolume:
52
Year:
2008
Language:
english
Pages:
7
DOI:
10.1016/j.sse.2007.07.031
File:
PDF, 413 KB
english, 2008