On-chip built-in jitter measurement circuit for PLL based...

Tsinghua Science & Technology 2007 Vol. 12; Iss. S1

On-chip built-in jitter measurement circuit for PLL based on duty-cycle modulation vernier delay line

Yu, Fei, Lee, Chung Len, Zhang, Jingkai
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Volume:
12
Year:
2007
Language:
english
Pages:
6
DOI:
10.1016/s1007-0214(07)70097-4
File:
PDF, 197 KB
english, 2007
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