Volume 26; Issue 4

IEEE Journal of Solid-State Circuits

Volume 26; Issue 4

1

A high-speed sample-and-hold technique using a Miller hold capacitance

Lim, P.J., Wooley, B.A.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 951 KB

english, 1991

2

An experimental 1.5-V 64-Mb DRAM

Nakagome, Y., Tanaka, H., Takeuchi, K., Kume, E., Watanabe, Y., Kaga, T., Kawamoto, Y., Murai, F., Izawa, R., Hisamoto, D., Kisu, T., Nishida, T., Takeda, E., Itoh, K.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 939 KB

english, 1991

3

A divided/shared bit-line sensing scheme for ULSI DRAM cores

Hidaka, H., Matsuda, Y., Fujishama, K.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 613 KB

english, 1991

4

A 12 MHz data cycle 4 Mb DRAM with pipeline operation

Kushiyama, N., Watanabe, Y., Oshawa, T., Muraoka, K., Nagahama, Y., Furuyama, T.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 565 KB

english, 1991

5

An experimental 4 Mb flash EEPROM with sector erase

McConnell, M., Ashmore, B., Bussey, R., Gill, M., Lin, S.-W., McElroy, D., Schreck, J.F., Shah, P., Stiegler, H., Truong, P., Esquivel, A.L., Paterson, J., Riemenschneider, B.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 974 KB

english, 1991

6

A 4 Mb NAND EEPROM with tight programmed Vt distribution

Momodomi, M., Tanaka, T., Iwata, Y., Tanaka, Y., Oodaira, H., Itoh, Y., Shirota, R., Ohuchi, K., Masuoka, F.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 632 KB

english, 1991

7

A 1 Mb EEPROM with MONOS memory cell for semiconductor disk application

Nozaki, T., Tanaka, T., Kijiya, Y., Kinoshita, E., Tsuchiya, T., Hayashi, Y.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 663 KB

english, 1991

8

An 8 ns 4 Mb serial access memory

Kuriyama, H., Hirose, T., Murakami, S., Wada, T., Fujita, K., Nishimura, Y., Anami, K.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 523 KB

english, 1991

9

A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy

Ohba, A., Ohbayashi, S., Shiomi, T., Takano, S., Anami, K., Honda, H., Ishigaki, Y., Hatanaka, M., Nagao, S., Kayano, S.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 748 KB

english, 1991

10

Fast-access BiCMOS SRAM architecture with a VSS generator

Douseki, T., Ohmori, Y., Yoshino, H., Yamada, J.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 477 KB

english, 1991

11

A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing

Nakase, Y., Suda, K., Mashiko, K., Ikeda, T., Kayano, S.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 713 KB

english, 1991

12

Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's

Seevinck, E., van Beers, P.J., Ontrop, H.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 958 KB

english, 1991

13

A dynamic three-state memory cell for high-density associative processors

Herrmann, F.P., Keast, C.L., Ishio, K., Wade, J.P., Sodini, C.G.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 529 KB

english, 1991

14

A high-speed clamped bit-line current-mode sense amplifier

Blalock, T.N., Jaeger, R.C.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 760 KB

english, 1991

15

Pipelined, time-sharing access technique for an integrated multiport memory

Endo, K., Matsumura, T., Yamada, J.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 643 KB

english, 1991

16

100-MHz serial access architecture for 4-Mb field memory

Miyauchi, M., Ikeda, H., Tsujimoto, A., Sato, Y., Tajima, J., Adachi, T., Hamaguchi, K., Fukuhara, N.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 513 KB

english, 1991

17

A circuit design of intelligent cache DRAM with automatic write-back capability

Arimoto, K., Asakura, M., Hidaka, H., Matsuda, Y., Fujishama, K.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 571 KB

english, 1991

18

Design of a second-level cache chip for shared-bus multimicroprocessor systems

Uchiyama, K., Aoki, H., Nishii, O., Hatano, S., Nagashima, O., Oishi, K., Kitano, J.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 642 KB

english, 1991

19

A fully operational 1 kb variable threshold Josephson RAM

Kurosawa, I., Nakagawa, H., Aoyagi, M., Kosaka, S., Takada, S.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 685 KB

english, 1991

20

Full-swing BiCMOS logic circuits with complementary emitter-follower driver configuration

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 740 KB

english, 1991

21

PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor

Kurita, K., Hotta, T., Nakano, T., Kitamura, N.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 462 KB

english, 1991

22

A 10 ns hybrid number system data execution unit for digital signal processing systems

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 1.01 MB

english, 1991

23

A 10 ns 54×54 b parallel structured full array multiplier with 0.5 μm CMOS technology

Mori, J., Nagamatsu, M., Hirano, M., Tanaka, S., Noda, M., Toyoshima, Y., Hashimoto, K., Hayashida, H., Maeguchi, K.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 774 KB

english, 1991

24

A self-learning neural network chip with 125 neurons and 10 K self-organization synapses

Arima, Y., Mashiko, K., Okada, K., Yamada, T., Maeda, A., Kondoh, H., Kayano, S.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 633 KB

english, 1991

25

Josephson macrocell array

Kotani, S., Inoue, A., Hasuo, S.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 640 KB

english, 1991

26

Second-order sigma-delta modulation for digital-audio signal acquisition

Brandt, B.P., Wingard, D.E., Wooley, B.A.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 1.01 MB

english, 1991

27

A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS

Lin, Y.-M., Kim, B., Gray, P.R.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 938 KB

english, 1991

28

A 10-b 70-MS/s CMOS D/A converter

Nakamura, Y., Miki, T., Maeda, A., Kondoh, H., Yazawa, N.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 621 KB

english, 1991

29

A highly sensitive on-chip charge detector for CCD area image sensor

Matsunaga, Y., Yamashita, H., Ohsawa, S.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 518 KB

english, 1991

30

Using cache mechanisms to exploit nonrefreshing DRAMs for on-chip memories

Lee, D.D., Katz, R.H.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 449 KB

english, 1991

31

NTL with complementary emitter-follower driver: a high-speed low-power push-pull logic circuit

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 458 KB

english, 1991

32

Multiemitter BiCMOS logic circuit family

Boudon, G., Mollier, P., Ong, I., Nuez, J.-P., Mauchauffee, D., Plassat, D., Simonet, J.-L., Wallart, F.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 550 KB

english, 1991

33

100-MHz monolithic low-pass filters with transmission zeros using NIC integrators

Takagi, S., Nitta, H., Koyama, J., Furihata, M., Fujii, N., Nagata, M., Yanagisawa, T.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 315 KB

english, 1991

34

Internal node probing of a DRAM with a low-temperature e-beam tester

Jenkins, K.A., Henkels, W.H.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 428 KB

english, 1991

35

Analysis and optimization of BiCMOS digital circuit structures

Embabi, S.H.K., Bellaouar, A., Elmasry, M.I.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 319 KB

english, 1991

36

A high-speed low-power JFET pull-down ECL circuit

Shin, H.J., Lu, P.-F., Chuang, C.-T.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 530 KB

english, 1991

37

Digitally programmable gain control circuit for charge-domain signal processing

Fossum, E.R., Kemeny, S.E., Bredthauer, R.A., LaShell, M.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1991

Language:

english

File:

PDF, 371 KB

english, 1991

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