IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

1

ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism

Rouying Zhan, Haigang Feng, Qiong Wu, Haolu Xie, Xiaokang Guan, Guang Chen, Wang, A.Z.H.

Journal:

Year:

2004

Language:

english

File:

PDF, 907 KB

english, 2004

2

Multiphase BIST: a new reseeding technique for high test-data compression

Kalligeros, E., Kavousianos, X., Nikolos, D.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2004

Language:

english

File:

PDF, 791 KB

english, 2004

3

Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip

Chunsheng Liu, Chakrabarty, K.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2004

Language:

english

File:

PDF, 927 KB

english, 2004

4

Network flow techniques for dynamic voltage scaling in hard real-time systems

Swaminathan, V., Chakrabarty, K.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2004

Language:

english

File:

PDF, 891 KB

english, 2004

5

MOOSE: a physically based compact DC model of SOI LD MOSFETs for analogue circuit simulation

D'Halleweyn, N.V.T., Benson, J., Redman-White, W., Mistry, K., Swanenberg, M.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2004

Language:

english

File:

PDF, 773 KB

english, 2004

6

A high-efficiency strongly self-checking asynchronous datapath

Jing-Ling Yang, Chiu-Sing Choy, Cheong-Fat Chan, Kong-Pong Pun

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2004

Language:

english

File:

PDF, 464 KB

english, 2004

7

Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains

Pomeranz, I.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2004

Language:

english

File:

PDF, 574 KB

english, 2004

8

Fault secure datapath synthesis using hybrid time and hardware redundancy

Kaijie Wu, Karri, R.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2004

Language:

english

File:

PDF, 522 KB

english, 2004

9

Noise-rejection model based on charge-transfer equation for digital CMOS circuits

Korshak, A.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2004

Language:

english

File:

PDF, 300 KB

english, 2004

10

Simple model of metal oxide varistor for Pspice Simulation

Zola, J.G.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2004

Language:

english

File:

PDF, 207 KB

english, 2004

11

A circuit-compatible model of ballistic carbon nanotube field-effect transistors

Raychowdhury, A., Mukhopadhyay, S., Roy, K.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2004

Language:

english

File:

PDF, 556 KB

english, 2004

12