IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

1

Fault diagnosis and logic debugging using Boolean satisfiability

Smith, A., Veneris, A., Ali, M.F., Viglas, A.

Journal:

Year:

2005

Language:

english

File:

PDF, 639 KB

english, 2005

2

An efficient heterogeneous tree multiplexer synthesis technique

Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2005

Language:

english

File:

PDF, 225 KB

english, 2005

3

Evaluating the reliability of NAND multiplexing with PRISM

Norman, G., Parker, D., Kwiatkowska, M., Shukla, S.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2005

Language:

english

File:

PDF, 362 KB

english, 2005

4

Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree

Saaied, H., Al-Khalili, D., Al-Khalili, A.J., Nekili, M.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2005

Language:

english

File:

PDF, 311 KB

english, 2005

5

Intra-task voltage scheduling on DVS-enabled hard real-time systems

Dongkun Shin, Jihong Kim

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2005

Language:

english

File:

PDF, 742 KB

english, 2005

6

Quasi-static scheduling of independent tasks for reactive systems

Cortadella, J., Kondratyev, A., Lavagno, L., Passerone, C., Watanabe, Y.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2005

Language:

english

File:

PDF, 900 KB

english, 2005

7

Schematic array models for associative and non-associative memory circuits

Bose, S., Nandi, A.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2005

Language:

english

File:

PDF, 379 KB

english, 2005

8

Combining ordered best-first search with branch and bound for exact BDD minimization

Ebendt, R., Gunther, W., Drechsler, R.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2005

Language:

english

File:

PDF, 506 KB

english, 2005

9

On reducing test application time for scan circuits using limited scan operations and transfer sequences

Yonsang Cho, Pomeranz, I., Reddy, S.M.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2005

Language:

english

File:

PDF, 292 KB

english, 2005

10

EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates

Rong Jiang, Wenyin Fu, Charlie Chung-Ping Chen

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2005

Language:

english

File:

PDF, 578 KB

english, 2005

11

Resource allocation for coarse-grain FPGA development

Eguro, K., Hauck, S.A.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2005

Language:

english

File:

PDF, 415 KB

english, 2005

12

A method for generating structurally aligned grids for semiconductor device simulation

Heitzinger, C., Sheikholeslami, A., Jong Mun Park, Selberherr, S.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2005

Language:

english

File:

PDF, 581 KB

english, 2005

13

A compact nonquasi-static MOSFET model based on the equivalent nonlinear transmission line

Pesic, T.V., Jankovic, N.D.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2005

Language:

english

File:

PDF, 572 KB

english, 2005

14