Volume 6; Issue 5

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IEEE Transactions on Computer-Aided Design of Integrated...
Volume 6; Issue 5

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volume 6; Issue 5

1

Editorial

Sangiovanni-Vincentelli, A.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 68 KB

english, 1987

2

On Delay Fault Testing in Logic Circuits

Chin Jen Lin, Reddy, S.M.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 1.54 MB

english, 1987

3

Accelerated Fault Simulation and Fault Grading in Combinational Circuits

Antreich, K.J., Schulz, M.H.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 1.31 MB

english, 1987

4

On the C-Testability of Generalized Counters

Chatterjee, A., Abraham, J.A.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 2.02 MB

english, 1987

5

Multiple-Valued Minimization for PLA Optimization

Rudell, R.L., Sangiovanni-Vincentelli, A.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 4.02 MB

english, 1987

6

Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 2.58 MB

english, 1987

7

Fast Methods for Switch-Level Verification of MOS Circuits

Reeves, D.S., Irwin, M.J.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 2.27 MB

english, 1987

8

A Scanline Data Structure Processor for VLSI Geometry Checking

Carlson, E.C., Rutenbar, R.A.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 2.55 MB

english, 1987

9

Optimal Chaining of CMOS Transistors in a Functional Cell

Wimer, S., Pinter, R.Y., Feldman, J.A.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 1.24 MB

english, 1987

10

An Efficient Approach to Gate Matrix Layout

Hwang, D.K., Fuchs, W.K., Sung Mo Kang

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 1.16 MB

english, 1987

11

Hierarchical Loose Routing for Gate Arrays

Winter, K., Mlynski, D.A.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 1.51 MB

english, 1987

12

Asymptotically Perfect Trivial Global Routing: A Stochastic Analysis

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 1.28 MB

english, 1987

13

Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout

Wei-Ming Dai, Kuh, E.S.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 1.52 MB

english, 1987

14

A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells

Casotto, A., Romeo, F., Sangiovanni-Vincentelli, A.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 1.58 MB

english, 1987

15

Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations

Rogers, W.A., Guzolek, J.F., Abraham, J.A.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 2.43 MB

english, 1987

16

Algorithmic Aspects of One-Dimensional Layout Compaction

Doenhardt, J., Lengauer, T.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 2.66 MB

english, 1987

17

Sensitivity Analysis for Device Design

Gnudi, A., Ciampolini, P., Guerrieri, R., Rudan, M., Baccarani, G.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 1.10 MB

english, 1987

18

Metal--Metal Matrix (M 3) for High-Speed MOS VLSI Layout

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 788 KB

english, 1987

19

Local Transformations via Cube Operations

Dietmeyer, D.L.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 1.58 MB

english, 1987

20

VLSI Layout Compaction with Grid and Mixed Constraints

Jin-Fuw Lee, Tang, D.T.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1987

Language:

english

File:

PDF, 1.33 MB

english, 1987

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