Volume 55; Issue 2

IEEE Transactions on Computers

Volume 55; Issue 2
1

[Front cover]

Year:
2006
Language:
english
File:
PDF, 136 KB
english, 2006
2

[Inside front cover]

Year:
2006
Language:
english
File:
PDF, 89 KB
english, 2006
3

[Back cover]

Year:
2006
Language:
english
File:
PDF, 136 KB
english, 2006
6

Ad

Year:
2006
File:
PDF, 1.96 MB
2006
7

TC Information for authors

Year:
2006
Language:
english
File:
PDF, 89 KB
english, 2006
9

Dynamic resizing of superscalar datapath components for energy efficiency

Year:
2006
Language:
english
File:
PDF, 1.52 MB
english, 2006
11

Global clock synchronization in sensor networks

Year:
2006
Language:
english
File:
PDF, 661 KB
english, 2006
13

InTeRail: a test architecture for core-based SOCs

Year:
2006
Language:
english
File:
PDF, 2.07 MB
english, 2006
14

Power-aware test planning in the early system-on-chip design exploration process

Year:
2006
Language:
english
File:
PDF, 1.57 MB
english, 2006
16

Testing embedded sequential cores in parallel using spectrum-based BIST

Year:
2006
Language:
english
File:
PDF, 1.20 MB
english, 2006
17

XPAND: an efficient test stimulus compression technique

Year:
2006
Language:
english
File:
PDF, 794 KB
english, 2006