IEEE Transactions on Very Large Scale Integration (VLSI) Systems

1

Passive Noise Shaping in SAR ADC With Improved Efficiency

Song, Yan, Chan, Chi-Hang, Zhu, Yan, Geng, Li, U, Seng-Pan, Martins, Rui Paulo

Journal:

Year:

2018

Language:

english

File:

PDF, 1.66 MB

english, 2018

2

Automatic Correction of Dynamic Power Management Architecture in Modern Processors

Sharafinejad, Reza, Alizadeh, Bijan, Navabi, Zainalabedin

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 2.73 MB

english, 2018

3

Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction

Li, Jiaqiang, Reviriego, Pedro, Xiao, Liyi, Argyrides, Costas, Li, Jie

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 3.40 MB

english, 2018

4

A Dual-Data Line Read Scheme for High-Speed Low-Energy Resistive Nonvolatile Memories

Lee, Albert, Lee, Hochul, Ebrahimi, Farbod, Lam, Bonnie, Chen, Wei-Hao, Chang, Meng-Fan, Amiri, Pedram Khalili, Wang, Kang-L.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 2.03 MB

english, 2018

5

The Low Area Probing Detector as a Countermeasure Against Invasive Attacks

Weiner, Michael, Manich, Salvador, Rodriguez-Montanes, Rosa, Sigl, Georg

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 1.90 MB

english, 2018

6

A High-Level Design Framework for the Automatic Generation of High-Throughput Systolic Binomial-Tree Solvers

Tavakkoli, Aryan, Thomas, David B.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 3.63 MB

english, 2018

7

A Scalable In-Memory Logic Synthesis Approach Using Memristor Crossbar

Gharpinde, Rahul, Thangkhiew, Phrangboklang Lynton, Datta, Kamalika, Sengupta, Indranil

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 4.32 MB

english, 2018

8

Physics-Based Compact TDDB Models for Low- $k$ BEOL Copper Interconnects With Time-Varying Voltage Stressing

Peng, Shaoyi, Zhou, Han, Kim, Taeyoung, Chen, Hai-Bao, Tan, Sheldon X.-D.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 2.21 MB

english, 2018

9

Provably Good Max–Min- $m$ -Neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication

Lin, Zhi-Wen, Fang, Shao-Yun, Chang, Yao-Wen, Rao, Wei-Cheng, Kuan, Chieh-Hsiung

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 6.02 MB

english, 2018

10

A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing

Ghanaatian, Reza, Balatsoukas-Stimming, Alexios, Muller, Thomas Christoph, Meidlinger, Michael, Matz, Gerald, Teman, Adam, Burg, Andreas

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 3.33 MB

english, 2018

11

The Implementation of the Improved OMP for AIC Reconstruction Based on Parallel Index Selection

Liu, Sujuan, Lyu, Ning, Wang, Haojiang

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 2.75 MB

english, 2018

12

ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling

Khavari Tavana, Mohammad, Hajkazemi, Mohammad Hossein, Pathak, Divya, Savidis, Ioannis, Homayoun, Houman

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 2.91 MB

english, 2018

14