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1

Fault tolerant system design and SEU injection based testing

Straka, Martin, Kastil, Jan, Kotasek, Zdenek, Miculka, Lukas

Journal:

Microprocessors and Microsystems

Year:

2013

Language:

english

File:

PDF, 1.65 MB

english, 2013

2

[IEEE 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) - Lubeck, Germany (2007.08.29-2007.08.31)] 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) - Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties

Skarvada, Jaroslav, Herrman, Tomas, Kotasek, Zdenek

Year:

2007

Language:

english

File:

PDF, 469 KB

english, 2007

3

[IEEE 2015 Euromicro Conference on Digital System Design (DSD) - Madeira, Portugal (2015.8.26-2015.8.28)] 2015 Euromicro Conference on Digital System Design - Software Fault Tolerance: The Evaluation by Functional Verification

Cekan, Ondrej, Podivinsky, Jakub, Kotasek, Zdenek

Year:

2015

Language:

english

File:

PDF, 164 KB

english, 2015

4

[IEEE 2018 21st Euromicro Conference on Digital System Design (DSD) - Prague, Czech Republic (2018.8.29-2018.8.31)] 2018 21st Euromicro Conference on Digital System Design (DSD) - Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller

Podivinsky, Jakub, Lojda, Jakub, Cekan, Ondrej, Kotasek, Zdenek

Year:

2018

Language:

english

File:

PDF, 642 KB

english, 2018

5

[IEEE 2019 IEEE Latin American Test Symposium (LATS) - Santiago, Chile (2019.3.11-2019.3.13)] 2019 IEEE Latin American Test Symposium (LATS) - Detecting hard synapses faults in artificial neural networks

Krcma, Martin, Kotasek, Zdenek, Lojda, Jakub

Year:

2019

Language:

english

File:

PDF, 417 KB

english, 2019

6

[IEEE 2019 IEEE Latin American Test Symposium (LATS) - Santiago, Chile (2019.3.11-2019.3.13)] 2019 IEEE Latin American Test Symposium (LATS) - Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems

Lojda, Jakub, Podivinsky, Jakub, Kotasek, Zdenek

Year:

2019

Language:

english

File:

PDF, 843 KB

english, 2019

7

[IEEE 2019 IEEE Latin American Test Symposium (LATS) - Santiago, Chile (2019.3.11-2019.3.13)] 2019 IEEE Latin American Test Symposium (LATS) - Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller

Podivinsky, Jakub, Lojda, Jakub, Kotasek, Zdenek

Year:

2019

Language:

english

File:

PDF, 323 KB

english, 2019

8

[IEEE 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS) - San Jose, Costa Rica (2020.2.25-2020.2.28)] 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS) - Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination

Podivinsky, Jakub, Cekan, Ondrej, Krcma, Martin, Burget, Radek, Hruska, Tomas, Kotasek, Zdenek

Year:

2020

File:

PDF, 133 KB

2020

9

Preface

Milan Češka, Zdeněk Kotásek, Mojmír Křetínský, Luděk Matyska, Tomáš Vojnar

Journal:

Electronic Notes in Theoretical Computer Science

Year:

2009

Language:

english

File:

PDF, 108 KB

english, 2009

10

Testability analysis based on the identification of testable blocks with predefined properties

Jaroslav Skarvada, Zdenek Kotasek, Tomas Herrman

Journal:

Microprocessors and Microsystems

Year:

2008

Language:

english

File:

PDF, 330 KB

english, 2008

11

[IEEE 2011 14th Euromicro Conference on Digital System Design (DSD) - Oulu, Finland (2011.08.31-2011.09.2)] 2011 14th Euromicro Conference on Digital System Design - SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems

Straka, Martin, Kastil, Jan, Kotasek, Zdenek

Year:

2011

Language:

english

File:

PDF, 254 KB

english, 2011

12

[Lecture Notes in Computer Science] Mathematical and Engineering Methods in Computer Science Volume 7119 || Rigorous System Design: The BIP Approach

Kotásek, Zdeněk, Bouda, Jan, Černá, Ivana, Sekanina, Lukáš, Vojnar, Tomáš, Antoš, David

Year:

2012

Language:

english

File:

PDF, 369 KB

english, 2012

13

[IEEE 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems - Vienna, Austria (2010.04.14-2010.04.16)] 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems - Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs

Straka, Martin, Kastil, Jan, Kotasek, Zdenek

Year:

2010

Language:

english

File:

PDF, 293 KB

english, 2010

14

[IEEE Systems (DDECS) - Cottbus, Germany (2011.04.13-2011.04.15)] 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems - Advanced fault tolerant bus for multicore system implemented in FPGA

Straka, Martin, Kastil, Jan, Novotny, Jaroslav, Kotasek, Zdenek

Year:

2011

Language:

english

File:

PDF, 516 KB

english, 2011

15

[Lecture Notes in Computer Science] Mathematical and Engineering Methods in Computer Science Volume 7119 ||

Kotásek, Zdeněk, Bouda, Jan, Černá, Ivana, Sekanina, Lukáš, Vojnar, Tomáš, Antoš, David

Year:

2012

Language:

english

File:

PDF, 3.42 MB

english, 2012

16

[IEEE 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Warsaw, Poland (2014.4.23-2014.4.25)] 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems - Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA

Miculka, Lukas, Kotasek, Zdenek

Year:

2014

Language:

english

File:

PDF, 181 KB

english, 2014

17

[IEEE 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Parma, Italy (2008.09.3-2008.09.5)] 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Digital Systems Architectures Based on On-line Checkers

Straka, Martin, Kotasek, Zdenek, Winter, Jan

Year:

2008

Language:

english

File:

PDF, 177 KB

english, 2008

18

[IEEE 2008 11th International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) - Bratislava, Slovakia (2008.04.16-2008.04.18)] 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems - Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration

Starecek, Lukas, Sekanina, Lukas, Kotasek, Zdenek

Year:

2008

Language:

english

File:

PDF, 433 KB

english, 2008

19

[IEEE 2012 15th Euromicro Conference on Digital System Design (DSD) - Cesme, Izmir, Turkey (2012.09.5-2012.09.8)] 2012 15th Euromicro Conference on Digital System Design - Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA

Kastil, Jan, Straka, Martin, Miculka, Lukas, Kotasek, Zdenek

Year:

2012

Language:

english

File:

PDF, 568 KB

english, 2012

20

[IEEE 2013 Euromicro Conference on Digital System Design (DSD) - Los Alamitos, CA, USA (2013.09.4-2013.09.6)] 2013 Euromicro Conference on Digital System Design - Methodology for Fault Tolerant System Design Based on FPGA into Limited Redundant Area

Miculka, Lukas, Straka, Martin, Kotasek, Zdenek

Year:

2013

Language:

english

File:

PDF, 250 KB

english, 2013

21

[IEEE 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools (DSD) - Patras, Greece (2009.08.27-2009.08.29)] 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools - High Availability Fault Tolerant Architectures Implemented into FPGAs

Straka, Martin, Kotasek, Zdenek

Year:

2009

Language:

english

File:

PDF, 316 KB

english, 2009

22

[IEEE 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) - Lubeck, Germany (2007.08.29-2007.08.31)] 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) - Online Protocol Testing for FPGA Based Fault Tolerant Systems

Tobola, Jiri, Kotasek, Zdenek, Korenek, Jan, Martinek, Tomas, Straka, Martin

Year:

2007

Language:

english

File:

PDF, 147 KB

english, 2007

23

[IEEE 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Tallinn, Estonia (2012.04.18-2012.04.20)] 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Test platform for fault tolerant systems design properties verification

Straka, Martin, Miculka, Lukas, Kastil, Jan, Kotasek, Zdenek

Year:

2012

Language:

english

File:

PDF, 198 KB

english, 2012

24

[IEEE 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) - Rome, Italy (2007.09.26-2007.09.28)] 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) - Checker Design for On-line Testing of Xilinx FPGA Communication Protocols

Straka, Martin, Tobola, Jiri, Kotasek, Zdenek

Year:

2007

Language:

english

File:

PDF, 301 KB

english, 2007

25

[IEEE 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD) - Lille, France (2010.09.1-2010.09.3)] 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools - Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration

Straka, Martin, Kastil, Jan, Kotasek, Zdenek

Year:

2010

Language:

english

File:

PDF, 202 KB

english, 2010

26

[IEEE 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Parma, Italy (2008.09.3-2008.09.5)] 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Power Conscious RTL Test Scheduling

Skarvada, Jaroslav, Kotasek, Zdenek, Herrman, Tomas

Year:

2008

Language:

english

File:

PDF, 280 KB

english, 2008

27

[IEEE Systems (DDECS) - Cottbus, Germany (2011.04.13-2011.04.15)] 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems - Decreasing test time by scan chain reorganization

Bartos, Pavel, Kotasek, Zdenek, Dohnal, Jan

Year:

2011

Language:

english

File:

PDF, 577 KB

english, 2011

28

[IEEE 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems - Vienna, Austria (2010.04.14-2010.04.16)] 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems - Reduction of power dissipation through parallel optimization of test vector and scan register sequences

Kotasek, Zdenek, Skarvada, Jaroslav, Strnadel, Josef

Year:

2010

Language:

english

File:

PDF, 326 KB

english, 2010

29

[IEEE 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD) - Lille, France (2010.09.1-2010.09.3)] 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools - The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption

Kotasek, Zdenek, karvada, Jaroslav, Strnadel, Josef

Year:

2010

Language:

english

File:

PDF, 420 KB

english, 2010

30

[IEEE 2014 17th Euromicro Conference on Digital System Design (DSD) - Verona, Italy (2014.8.27-2014.8.29)] 2014 17th Euromicro Conference on Digital System Design - State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System

Szurman, Karel, Miculka, Lukas, Kotasek, Zdenek

Year:

2014

Language:

english

File:

PDF, 167 KB

english, 2014

31

[IEEE 2014 17th Euromicro Conference on Digital System Design (DSD) - Verona, Italy (2014.8.27-2014.8.29)] 2014 17th Euromicro Conference on Digital System Design - Automatic Construction of On-line Checking Circuits Based on Finite Automata

Matuova, Lucie, Katil, Jan, Kotasek, Zdenek

Year:

2014

Language:

english

File:

PDF, 212 KB

english, 2014

32

[IEEE 2014 17th Euromicro Conference on Digital System Design (DSD) - Verona, Italy (2014.8.27-2014.8.29)] 2014 17th Euromicro Conference on Digital System Design - The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical Applications

Podivinsky, Jakub, Cekan, Ondrej, Simkova, Marcela, Kotasek, Zdenek

Year:

2014

Language:

english

File:

PDF, 380 KB

english, 2014

33

[IEEE 2010 NORCHIP - Tampere, Finland (2010.11.15-2010.11.16)] NORCHIP 2010 - Generic partial dynamic reconfiguration controller for fault tolerant designs based on FPGA

Straka, Martin, Kastil, Jan, Kotasek, Zdenek

Year:

2010

Language:

english

File:

PDF, 108 KB

english, 2010

34

The evaluation platform for testing fault-tolerance methodologies in electro-mechanical applications

Podivinsky, Jakub, Cekan, Ondrej, Simkova, Marcela, Kotasek, Zdenek

Journal:

Microprocessors and Microsystems

Year:

2015

Language:

english

File:

PDF, 2.83 MB

english, 2015

35

[IEEE 2014 9th International Conference on Computer Engineering & Systems (ICCES) - Cairo, Egypt (2014.12.22-2014.12.23)] 2014 9th International Conference on Computer Engineering & Systems (ICCES) - Towards a state synchronization methodology for recovery process after partial reconfiguration of fault tolerant systems

Szurman, Karel, Miculka, Lukas, Kotasek, Zdenek

Year:

2014

Language:

english

File:

PDF, 511 KB

english, 2014

36

Evolution of synthetic RTL benchmark circuits with predefined testability

Pecenka, Tomas, Sekanina, Lukas, Kotasek, Zdenek

Journal:

ACM Transactions on Design Automation of Electronic Systems

Year:

2008

Language:

english

File:

PDF, 491 KB

english, 2008

37

[IEEE 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Belgrade, Serbia (2015.4.22-2015.4.24)] 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems - Mapping Trained Neural Networks to FPNNs

Krcma, Martin, Kastil, Jan, Kotasek, Zdenek

Year:

2015

Language:

english

File:

PDF, 173 KB

english, 2015

38

[IEEE 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Belgrade, Serbia (2015.4.22-2015.4.24)] 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems - Application of Evolutionary Algorithms for Regression Suites Optimization

Beleova, Michaela, Kotasek, Zdenek, imkova, Marcela, Hruka, Toma

Year:

2015

Language:

english

File:

PDF, 143 KB

english, 2015

39

[IEEE 2015 Euromicro Conference on Digital System Design (DSD) - Madeira, Portugal (2015.8.26-2015.8.28)] 2015 Euromicro Conference on Digital System Design - Automation and Optimization of Coverage-driven Verification

imkova, Marcela, Kotasek, Zdenek

Year:

2015

Language:

english

File:

PDF, 1.18 MB

english, 2015

40

[IEEE 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Belgrade, Serbia (2015.4.22-2015.4.24)] 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems - FPGA Prototyping and Accelerated Verification of ASIPs

Podivinsky, Jakub, imkova, Marcela, Cekan, Ondrej, Kotasek, Zdenek

Year:

2015

Language:

english

File:

PDF, 197 KB

english, 2015

41

[IEEE 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) - Oslo, Norway (2015.10.26-2015.10.28)] 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) - Fault tolerant Field Programmable Neural Networks

Krcma, Martin, Kotasek, Zdenek, Kastil, Jan

Year:

2015

Language:

english

File:

PDF, 98 KB

english, 2015

42

[IEEE 2016 Euromicro Conference on Digital System Design (DSD) - Limassol, Cyprus (2016.8.31-2016.9.2)] 2016 Euromicro Conference on Digital System Design (DSD) - Regression Test Suites Optimization for Application-specific Instruction-Set Processors and Their Use for Dependability Analysis

Zachariaova, Marcela, Kekelyova-Beleova, Michaela, Kotasek, Zdenek

Year:

2016

Language:

english

File:

PDF, 257 KB

english, 2016

43

[IEEE 2016 Euromicro Conference on Digital System Design (DSD) - Limassol, Cyprus (2016.8.31-2016.9.2)] 2016 Euromicro Conference on Digital System Design (DSD) - Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems

Podivinsky, Jakub, Cekan, Ondrej, Lojda, Jakub, Kotasek, Zdenek

Year:

2016

Language:

english

File:

PDF, 462 KB

english, 2016

44

[IEEE 2016 International Conference on Field-Programmable Technology (FPT) - Xi'an, China (2016.12.7-2016.12.9)] 2016 International Conference on Field-Programmable Technology (FPT) - Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAs

Podivinsky, Jakub, Cekan, Ondrej, Lojda, Jakub, Kotasek, Zdenek

Year:

2016

Language:

english

File:

PDF, 157 KB

english, 2016

45

[IEEE 2016 International Conference on Field-Programmable Technology (FPT) - Xi'an, China (2016.12.7-2016.12.9)] 2016 International Conference on Field-Programmable Technology (FPT) - Random stimuli generation based on a stochastic context-free grammar

Cekan, Ondrej, Podivinsky, Jakub, Kotasek, Zdenek

Year:

2016

Language:

english

File:

PDF, 67 KB

english, 2016

46

[IEEE 2016 International Conference on Field-Programmable Technology (FPT) - Xi'an, China (2016.12.7-2016.12.9)] 2016 International Conference on Field-Programmable Technology (FPT) - HLS-based fault tolerance approach for SRAM-based FPGAs

Lojda, Jakub, Podivinsky, Jakub, Krcma, Martin, Kotasek, Zdenek

Year:

2016

Language:

english

File:

PDF, 101 KB

english, 2016

47

[IEEE 2016 International Conference on Field-Programmable Technology (FPT) - Xi'an, China (2016.12.7-2016.12.9)] 2016 International Conference on Field-Programmable Technology (FPT) - Implementation of fault tolerant techniques into FPNNs

Krcma, Martin, Kotasek, Zdenek, Lojda, Jakub

Year:

2016

Language:

english

File:

PDF, 775 KB

english, 2016

48

Partial Scan Methodologies-A Survey

Kotásek, Zdeněk, Růžička, Richard

Journal:

IFAC Proceedings Volumes

Year:

2000

Language:

english

File:

PDF, 1.17 MB

english, 2000

49

Feedback Loops Detection for RT Circuit Test Application Purposes Based on an Algebraic Method

Mika, Daniel, Kotásek, Zdenĕk

Journal:

IFAC Proceedings Volumes

Year:

2003

Language:

english

File:

PDF, 594 KB

english, 2003

50

[IEEE 2017 IEEE East-West Design & Test Symposium (EWDTS) - Novi Sad (2017.9.29-2017.10.2)] 2017 IEEE East-West Design & Test Symposium (EWDTS) - Redundant data types and operations in HLS and their use for a robot controller unit fault tolerance evaluation

Lojda, Jakub, Podivinsky, Jakub, Kotasek, Zdenek

Year:

2017

Language:

english

File:

PDF, 158 KB

english, 2017