Memory-cell layout as a factor in the single-event-upset...

Russian Microelectronics 2011 / 05 Vol. 40; Iss. 3

Memory-cell layout as a factor in the single-event-upset susceptibility of submicron dice CMOS SRAM

V. Ya. Stenin, I. G. Cherkasov
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Volume:
40
Language:
english
Pages:
6
DOI:
10.1134/s1063739711030097
Date:
May, 2011
File:
PDF, 273 KB
english, 2011
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