Design methodology and optimization of gate-driven NMOS ESD...

IEEE Transactions on Electron Devices 1998 Vol. 45; Iss. 12

Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes

Chen, J.Z., Amerasekera, E.A., Duvvury, C.
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Volume:
45
Year:
1998
Language:
english
Pages:
9
DOI:
10.1109/16.735721
File:
PDF, 510 KB
english, 1998
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