Logic and memory with nanocell circuits

IEEE Transactions on Electron Devices 2003 Vol. 50; Iss. 9

Logic and memory with nanocell circuits

Husband, C.P., Husband, S.M., Daniels, J.S., Tour, J.M.
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Volume:
50
Year:
2003
Language:
english
Pages:
11
DOI:
10.1109/ted.2003.815860
File:
PDF, 1.37 MB
english, 2003
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