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A physically based compact gate C-V model for ultrathin (EOT ∼1 nm and below) gate dielectric MOS devices
Fei Li, Mudanai, S., Register, L.F., Banerjee, S.K.Volume:
52
Year:
2005
Language:
english
Pages:
11
DOI:
10.1109/ted.2005.848079
File:
PDF, 592 KB
english, 2005