Characterization and Implementation of Fault-Tolerant...

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2011 Vol. 30; Iss. 1

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip

Loi, I., Angiolini, F., Fujita, S., Mitra, S., Benini, L.
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Volume:
30
Year:
2011
Language:
english
DOI:
10.1109/tcad.2010.2065990
File:
PDF, 1.19 MB
english, 2011
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