Buffer Sizing and Polarity Assignment in Clock Tree...

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2011 Vol. 30; Iss. 1

Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization

Hochang Jang, Deokjin Joo, Taewhan Kim
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Volume:
30
Year:
2011
Language:
english
DOI:
10.1109/tcad.2010.2066650
File:
PDF, 1.14 MB
english, 2011
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