Efficient Shuffled Decoder Architecture for Nonbinary...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2013 / 09 Vol. 21; Iss. 9

Efficient Shuffled Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes

Lin, Jun, Yan, Zhiyuan
How much do you like this book?
What’s the quality of the file?
Download the book for quality assessment
What’s the quality of the downloaded files?
Volume:
21
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/tvlsi.2012.2218839
Date:
September, 2013
File:
PDF, 728 KB
english, 2013
Conversion to is in progress
Conversion to is failed