FinCANON: A PVT-Aware Integrated Delay and Power Modeling...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2014 / 5 Vol. 22; Iss. 5

FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks

Chun-Yi Lee,, Jha, Niraj K.
How much do you like this book?
What’s the quality of the file?
Download the book for quality assessment
What’s the quality of the downloaded files?
Volume:
22
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2013.2260569
Date:
May, 2014
File:
PDF, 3.18 MB
english, 2014
Conversion to is in progress
Conversion to is failed