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FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks
Chun-Yi Lee,, Jha, Niraj K.Volume:
22
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2013.2260569
Date:
May, 2014
File:
PDF, 3.18 MB
english, 2014