IEEE Transactions on Very Large Scale Integration (VLSI) Systems

1

Rate-0.96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory

Jonghong Kim,, Wonyong Sung,

Journal:

Year:

2014

Language:

english

File:

PDF, 3.32 MB

english, 2014

2

FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks

Chun-Yi Lee,, Jha, Niraj K.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 3.18 MB

english, 2014

3

Dark Silicon Aware Multicore Systems: Employing Design Automation With Architectural Insight

Allred, Jason M., Roy, Sanghamitra, Chakraborty, Koushik

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 379 KB

english, 2014

4

A 12.5-Gb/s On-Chip Oscilloscope to Measure Eye Diagrams and Jitter Histograms of High-Speed Signals

Dehlaghi, Behzad, Magierowski, Sebastian, Belostotski, Leonid

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 4.43 MB

english, 2014

5

Light-Weight On-Chip Structure for Measuring Timing Uncertainty Induced by Noise in Integrated Circuits

Shuo Wang,, Tehranipoor, Mohammad

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 1.38 MB

english, 2014

6

Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority

Min-Woo Lee,, Ji-Hwan Yoon,, Jongsun Park,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 1.51 MB

english, 2014

7

Design of On-Chip Lightweight Sensors for Effective Detection of Recycled ICs

Xuehui Zhang,, Tehranipoor, Mohammad

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 1.77 MB

english, 2014

8

Logical Effort for CMOS-Based Dual Mode Logic Gates

Levi, Itamar, Belenky, Alexander, Fish, Alexander

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 1.97 MB

english, 2014

9

Average-8T Differential-Sensing Subthreshold SRAM With Bit Interleaving and 1k Bits Per Bitline

Khayatzadeh, Mahmood, Yong Lian,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 2.53 MB

english, 2014

10

UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors

Xiaowen Wu,, Yaoyao Ye,, Jiang Xu,, Wei Zhang,, Weichen Liu,, Nikdast, Mahdi, Xuan Wang,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 1.89 MB

english, 2014

11

LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology

Junwhan Ahn,, Kiyoung Choi,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 558 KB

english, 2014

12

On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time

Yansheng Wang,, Leibo Liu,, Shouyi Yin,, Min Zhu,, Peng Cao,, Jun Yang,, Shaojun Wei,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 1.53 MB

english, 2014

13

High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology

Ching-Che Chung,, Duo Sheng,, Sung-En Shen,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 4.06 MB

english, 2014

14

Built-In Binary Code Inversion Technique for On-Chip Flash Memory Sense Amplifier With Reduced Read Current Consumption

Daejin Park,, Tag Gon Kim,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 1.56 MB

english, 2014

15

Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over ${\rm GF}(2^{m})$

Mozaffari-Kermani, Mehran, Azarderakhsh, Reza, Chiou-Yng Lee,, Bayat-Sarmadi, Siavash

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 642 KB

english, 2014

16

Area-Delay Efficient Binary Adders in QCA

Perri, Stefania, Corsonello, Pasquale, Cocorullo, Giuseppe

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 1.12 MB

english, 2014

17

High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives

Youngjoo Lee,, Hoyoung Yoo,, Injae Yoo,, In-Cheol Park,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 774 KB

english, 2014

18

Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization

Tseng-Chin Luo,, Chao, Mango C-T, Huan-Chi Tseng,, Goto, Masaharu, Fisher, Philip A., Yuan-Yao Chang,, Chi-Min Chang,, Takao, Takayuki, Iwasaki, Katsuhito, Cheng Mao Lee,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 1.40 MB

english, 2014

19

1.9-ps Jitter, 10.0-dBm-EMI Reduction Spread-Spectrum Clock Generator With Autocalibration VCO Technique for Serial-ATA Application

Kawamoto, Takashi, Suzuki, Masato, Noto, Takayuki

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 2.59 MB

english, 2014

20

Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method

Yuan Li,, Chow, Paul, Jiang Jiang,, Minxuan Zhang,, Shaojun Wei,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 1.35 MB

english, 2014

21

1-V 365- $\mu{\rm W}$ 2.5-MHz Channel Selection Filter for 3G Wireless Receiver in 55-nm CMOS

Tien-Yu Lo,, Chi-Hsiang Lo,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 1007 KB

english, 2014

22

Nonvolatile CBRAM-Crossbar-Based 3-D-Integrated Hybrid Memory for Data Retention

Yuhao Wang,, Hao Yu,, Wei Zhang,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 2.49 MB

english, 2014

23

Litho-Friendly Decomposition Method for Self-Aligned Triple Patterning

Mirsaeedi, Minoo, Torres, Andres J., Anis, Mohab

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 1.84 MB

english, 2014

24

Low-Complexity Reconfigurable Fast Filter Bank for Multi-Standard Wireless Receivers

Darak, Sumit J., Gopi, Smitha Kavallur Pisharath, Prasad, Vinod Achutavarrier, Lai, Edmund

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 1.88 MB

english, 2014

25

Optimization Scheme to Minimize Reference Resistance Distribution of Spin-Transfer-Torque MRAM

Kejie Huang,, Ning Ning,, Yong Lian,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 656 KB

english, 2014

26

Variation-Aware Variable Latency Design

Gupta, Saket, Sapatnekar, Sachin S.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 2.62 MB

english, 2014

27

Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer

Wen-Hsiang Chang,, Chao, Mango C.-T, Shi-Hao Chen,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 3.02 MB

english, 2014

28